- Utilizing heterogeneous computing to accelerate scientific applications
- Performance optimization
- Performance portability
- Complex system simulation
- Promoting diversity in RSE and HPC communities
I am a GPU developer advocate at NVIDIA helping to bring GPU and HPC to a growing user community in Europe and around the world. I am a community builder with a passion for open-source software and is actively involved in the HPC and RSE communities. As a Software Sustainability Institute Fellow, and Research Software Engineer (RSE) advocate, I am actively promoting reproducible and sustainable software, use of HPC and particularly GPUs through training, seminars, research software consultancy, and outreach.
Prior to joining Nvidia, I was a Research Software Engineer in Massive Scale Complex Systems Simulation with Accelerated Computing at the University of Sheffield, UK. I worked in the area of complex system modelling using emerging high-performance parallel architectures focusing on development of the next version of FLAMEGPU (Flexible Large Scale Agent-Based Simulation Framework) software, which allows complex systems modelling on GPUs by abstracting away the complexity of the GPU architecture.
As a STEM advocate, I am actively involved in outreach programs to encourage and empower minorities' involvement at all levels within the HPC sector and to promote equality and diversity in both HPC and RSE communities. I am a long-standing Women in HPC volunteer, including leading WHPC’s workshop last year and this year at International Supercomputing Conference. I chaired several technical and scientific conferences and served as a committee member of high profile HPC conferences.
In my previous appointment as a software developer at the School of Computer Science, University of Glasgow, my role was to accelerate vision algorithm for robots eye making contribution to a multi-disciplinary European project, named CloPeMa(Clothes Perception and Manipulation). During this project, I helped to develop and accelerate the stereo matching algorithm utilizing parallel architectures (GPU & Multicore CPU).
My doctoral work at the University of Glasgow involved research in high-performance logic gate level circuit simulation targeting modern parallel processors (multicore, GPU & heterogeneous platforms). I developed software and a parser to address the performance challenges of software simulators by leveraging multi-core and many-core architectures.
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Check out contributions by and mentions of Mozhgan Kabiri Chimeh on www.software.ac.uk